Espressif Systems /ESP32-P4 /SPI1 /SPI_MEM_INT_RAW

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Interpret as SPI_MEM_INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_PER_END_INT_RAW)SPI_MEM_PER_END_INT_RAW 0 (SPI_MEM_PES_END_INT_RAW)SPI_MEM_PES_END_INT_RAW 0 (SPI_MEM_WPE_END_INT_RAW)SPI_MEM_WPE_END_INT_RAW 0 (SPI_MEM_SLV_ST_END_INT_RAW)SPI_MEM_SLV_ST_END_INT_RAW 0 (SPI_MEM_MST_ST_END_INT_RAW)SPI_MEM_MST_ST_END_INT_RAW 0 (SPI_MEM_BROWN_OUT_INT_RAW)SPI_MEM_BROWN_OUT_INT_RAW

Description

SPI1 interrupt raw register

Fields

SPI_MEM_PER_END_INT_RAW

The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.

SPI_MEM_PES_END_INT_RAW

The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.

SPI_MEM_WPE_END_INT_RAW

The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.

SPI_MEM_SLV_ST_END_INT_RAW

The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others

SPI_MEM_MST_ST_END_INT_RAW

The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.

SPI_MEM_BROWN_OUT_INT_RAW

The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.

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